This application relies for priority upon Korean Patent Application No. 2002-744, filed on Jan. 7, 2002, the contents of which are herein incorporated by reference in their entirety.
The present invention relates to a semiconductor device and method of fabricating the same, and more specifically to a dynamic random access memory (DRAM) device having a resistor and method of fabricating the same.
Generally, a DRAM device comprises a cell array area and a peripheral circuit area. The cell array area includes a plurality of unit cells, each of which comprises a MOS transistor and a storage capacitor. The storage capacitor comprises a lower electrode (i.e., storage node) and an upper electrode (i.e., plate node). It is a generally accepted fact in industry that the capacitance of the storage capacitor is required to be 0.25 xcexcF or more, while the unit cell size has been constantly reduced for higher packing density of a DRAM device. One of approaches used to retain the required value of the capacitance is to increase the height of the storage capacitor. Especially in the case of a DRAM device with single cylinder type storage nodes and a design rule of 0.15 xcexcm, the height of the storage node is required to be about 1.4 xcexcm or more. The increased height of the storage node induces an increased step difference between the cell array area and the peripheral circuit area in the DRAM device.
Meanwhile, resistors are widely used in semiconductor memory devices including DRAM devices. The resistors are usually formed in the peripheral circuit area of a semiconductor memory device. One example of an application of the resistors is a circuit for converting an external voltage level into an internal voltage level. In DRAM devices, the resistors are usually formed of the same material as the plate node and are formed at the same process step for forming the plate node. In detail, a plate node layer is formed on storage nodes and a peripheral circuit area. The plate node layer is patterned to form a plate node on the storage nodes and resistors on the peripheral circuit area simultaneously.
However, in recent DRAM devices having high packing density, the patterns of the resistors are not fine. That is, it is very difficult to maintain uniformity in the widths of the resistors. The irregular widths induce irregular resistance of the resistors. As a result, abnormal operations of the DRAM devices may occur. The width irregularity problem is mainly due to the above-mentioned step difference between the cell array area and the peripheral circuit area.
The irregularity problem may be relieved by using a well-known advanced photolithography process that is able to pattern the plate node layer into quite fine patterns of resistors in spite of the increased step difference. However, the cost of the advanced process is too expensive such that it cannot be widely accepted in industry. Accordingly, the need to relieve the width irregularity problem without substantially increasing the cost for patterning the plate node layer remains.
It is an object of the present invention to provide a method for forming a semiconductor device, wherein resistors on the peripheral circuit area have substantially uniform widths without substantially increasing the cost for patterning the plate node layer.
It is another object of the present invention to provide a method for forming a DRAM device, wherein resistors on the peripheral circuit area have substantially uniform resistance values without substantially increasing the cost for patterning the plate node layer.
It is another object of the present invention to provide a semiconductor device, wherein resistors on the peripheral circuit area have substantially uniform widths and resistance values so as to substantially avoid abnormal operations of the semiconductor device.
According to one aspect of the present invention, a method of fabricating a semiconductor device is provided. The method comprises forming a mold layer on a substrate. The mold layer is patterned to form a plurality of first molding holes, a second molding hole and a third molding hole in the mold layer. A storage node layer is formed on the mold layer as well as in the first, second and third molding holes. A portion of the storage node layer is removed to form a plurality of storage nodes, a first portion of a resistor and a first portion of a conductive stud in the first, second and third molding holes respectively. The first portion of the resistor and the first portion of the stud are formed of the storage node layer material. Each of the storage nodes has an inner wall and an outside wall. A portion of the mold layer is removed, thereby exposing a portion of the outside wall and leaving a remaining portion of the mold layer in the peripheral circuit area. The portion of the mold layer is interposed between each of the storage nodes. The remaining portion of the mold layer has the second molding hole therethrough. A capacitor dielectric layer is formed on the storage nodes and the remaining portion of the mold layer. A plate node layer is formed on the capacitor dielectric layer. The plate node layer is patterned to form a plate node on the plurality of storage nodes. The plate node layer may be formed in the second or third molding holes to fill the second or third molding hole. The capacitor dielectric layer may also be formed in the second or third molding holes.
According to another aspect of the present invention, a method of fabricating a semiconductor device is provided. The method comprises providing a substrate and defining a first area and a second area in the substrate. A mold layer is formed on the substrate and in the first and second areas. An anti-reflective layer is formed on the mold layer. A first portion of the anti-reflective layer is selectively etched, thereby reducing the thickness of the anti-reflective layer in the first area. The first portion of the anti-reflective layer is located in the first area. First molding holes and a second molding hole are formed in the first area and second area respectively by patterning the mold layer and the anti-reflective layer. A second portion of the anti-reflective layer is etched to leave a remaining portion of the anti-reflective layer only in the second area. A storage node layer is formed on the mold layer as well as in the first and second molding holes. A plurality of storage nodes and a first portion of a resistor are formed in the first molding holes and in the second molding hole respectively by removing a portion of the storage node layer. The first portion of a resistor is formed of the storage node layer. Each of the storage nodes has an inner wall and an outside wall. A portion of the mold layer is etched by using the remaining portion of the anti-reflective layer as a etch mask, thereby exposing a portion of the outside wall and leaving a remaining portion of the mold layer in the second area. A portion of the mold layer is located in the first area. The remaining portion of the mold layer has the second molding hole therethrough.
According to another aspect of the present invention, a semiconductor device is provided. The semiconductor device comprises a plurality of storage nodes on a substrate. A mold layer is formed on the substrate. The mold layer surrounds the plurality of storage nodes in plan view. A resistor is formed through the mold layer. The resistor comprises a material of the storage nodes. The height of the plurality of storage nodes is substantially same as the thickness of the mold layer. The height of the resistor is substantially same as the thickness of the mold layer. A plate node is formed on the plurality of storage nodes. A capacitor dielectric layer is formed between the plurality of storage nodes and the plate node. The resistor may further comprise a material of the plate node or a material of the capacitor dielectric layer.
A conductive stud is formed through the mold layer. The stud comprises a material of the storage nodes. The height of the plurality of storage nodes is substantially same as the height of the stud.
According to another aspect of the present invention, a semiconductor device is provided. The semiconductor device comprises a mold layer on the substrate. The mold layer comprises a recess region. A resistor is formed in the recess region.